A commercial ASIC flow is mostly a licensing problem. Tool seats, PDK access and the NDAs around them are what keep a student team out — not the engineering. We went the other way: an entirely open flow, OpenLane onto the SkyWater SKY130 open PDK, and no licence to pay for at any step.
Two hardened runs, not one
The first run hardened the standalone MCU on the
demo_v04 design. The final run took the full top-level
SoC, AI accelerator included, after demo_v10. Both are
complete RTL-to-GDS passes: floorplanning, macro placement, power ring and
routing.
Doing it twice mattered more than doing it once. The first run is where you find out which parts of your RTL the flow refuses to place; the second is where you find out whether you actually fixed them.
Where the performance comes from
An open flow does not hand you performance. What it hands you is every knob, unlocked, and the willingness to run the flow enough times to learn which ones matter. Our gains came out of floorplan and macro placement work rather than out of the synthesis settings — where the memories sit relative to the core decides how much of the critical path is wire.
Measured, three ways
The same RTL, built for all three targets and measured on each:
| Agilex 3 | SKY130A | Gowin GW2A | |
|---|---|---|---|
| Kind | FPGA | ASIC | FPGA |
| Tech node | Intel 7 | SkyWater 130 nm | TSMC 55 nm |
| ALM / LUT / cells | 8,015 | 60,249 | 17,440 |
| Registers | 7,217 | 8,065 | 5,113 |
| Fmax | 130 MHz | 71.4 MHz | 36 MHz |
| Power | 84.2 mW | 110 mW (core only) | 280 mW |
| State | Demo implemented | Signoff ready | Demo implemented |
The comparison that matters is the middle column against the right one. A 130 nm open PDK, hardened with open-source tools and no licence fees, runs the same design at nearly double the clock of the 55 nm commercial FPGA beside it, on 39% of the power. Against Agilex 3 on Intel 7 it gives up clock, as three process generations would suggest — and still lands within a factor of two.
What it cost
Nothing, in licence terms. The entire physical implementation path — synthesis, floorplanning, placement, routing, sign-off checks and GDS — runs on open-source tooling against an open PDK. For a team of three first-year students, that is the difference between a tape-out-ready design and a block diagram.
Reproducing it
Both runs are scripted rather than clicked: the configuration lives with the design, so the flow can be re-run from a clean checkout instead of being reconstructed from someone's shell history.