The team
Three engineers at Hacettepe University, mostly self-taught in digital design, building a RISC-V SoC from RTL to silicon.
Bekir YUFKA
System Architect & Project Lead- Top-level synthesis of the MCU subsystem
- System-wide UVM verification
- AI accelerator designer
Eyüp Ertan SAĞDIŞ
Core Design & Integration Engineer- AXI4 / AXI4-Lite interconnect architect
- Most peripheral modules in SystemVerilog
- ASIC flow — OpenLane on SKY130A
Arda TECİMEN
Verification & Debug Infrastructure Engineer- Module-level SystemVerilog testbenches
- UVM verification and top-level testbench
- JTAG debug interface, IVC block, pinmux
- Custom boot sequencing and init flows