About
Eyüp designed the interconnect that everything else in the SoC hangs off — the AXI4 / AXI4-Lite fabric — and implemented most of the peripheral modules that attach to it. He also works on RISC-V core integration. Beyond the RTL, he ran the ASIC flow: both OpenLane hardening runs on SKY130A, floorplanning, macro placement, power ring and routing.
Responsibilities
- Self-learner, focused on HDL and architecture
- Implemented most peripheral modules in SystemVerilog
- Architect of the AXI4 / AXI4-Lite interconnect
- Works on RISC-V core integration and operation
- Ran the ASIC flow — OpenLane on SKY130A, RTL to GDS