Blog

Engineering write-ups on the parts of the chip we build ourselves — the MCU subsystem, the AI accelerator, verification, and both silicon flows.

RISC-V microcontroller subsystems end-to-end: AXI4-Lite fabric, clock/reset strategy, and bring-up.

A custom neural-network inference engine with its own register interface, weight ROMs, and two design iterations.

JTAG, an interrupt vector controller and a pinmux, added at demo_v06 — the hardware that makes bring-up something other than guesswork.

Two deliberately independent verification paths — and the real bug the second one caught.

The same RTL built on Agilex 3 and Gowin FPGAs and carried through OpenLane to a hardened GDS.

Hardening a RISC-V SoC on SKY130 with an entirely open flow — no tool licences, no PDK fees.