The same RTL is carried through three implementation targets: two FPGA families from different vendors, and an open-source ASIC flow. None of them is a simulation-only exercise: each produces real, buildable output.
FPGA — Altera Agilex 3
Built through Quartus Prime, from the same SystemVerilog that goes to OpenLane. A bug found on the board is a bug in the RTL we harden, not in an FPGA-only fork of it.
FPGA — Gowin
The second FPGA target, with Gowin-specific HDMI and RAM IP wrappers. It is useful precisely because it is cheap — it lowers the cost of having hardware in more than one pair of hands.
ASIC — OpenLane, RTL to GDS
A real open-source physical design flow, not a paper exercise. There are completed hardened runs for both a standalone MCU and the full top-level SoC, including macro placement, power ring and routing, and floorplanning.
The two runs sit at different points in the version history. The first
hardened the standalone MCU on the demo_v04 design; the final run
took the full top-level SoC — AI accelerator included — after
demo_v10.
Getting a design through hardening is where a lot of otherwise-working RTL falls over, which is why we treat it as a first-class target rather than a stretch goal.
Simulation — Vivado
Vivado is our simulator, not an implementation target. A TCL script builds the Vivado project non-interactively on Windows or Linux, and simulation runs directly from the Vivado TCL console — so a reviewer can reproduce the run without clicking through a GUI.
A packaged, self-contained demo is provided for the competition jury: the Vivado project, the build scripts, and guides in both English and Turkish.
Why three targets at once
An FPGA tells you the design is functionally correct. A hardening run tells you it is physically buildable. They fail for different reasons, and a design that passes only one of them is not finished. Keeping all three flows live from the same RTL means none of them can quietly rot.