SiliCore

Altera Agilex 3

Our Altera FPGA target, built through Quartus Prime from the same SystemVerilog that goes to OpenLane.

AlteraQuartus Prime FPGA target
Placeholder Altera Agilex 3 artwork — to be replaced with a photograph.

Agilex 3 is one of the two FPGA families the SoC is built for. Nothing is forked for it: the RTL that synthesises here is the RTL that goes through OpenLane, so a bug caught on the board is a bug in the design rather than in an FPGA-only variant of it.

Results

Agilex 3 is the fastest of the three targets: the design closes at 130 MHz and draws 84.2 mW, using 8,015 ALMs and 7,217 registers. The demo is implemented and running on hardware.