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TEKNOFEST 2026 · Chip Design

A RISC-V microcontroller, built around CV32E40P

SiliCore is a student-born engineering team in Türkiye that took a 32-bit RISC-V SoC all the way from SystemVerilog RTL to three implementation targets — Agilex 3 and Gowin FPGAs, and a real open-source ASIC tapeout flow.

Explore the architecture See our progress

4^th

of 94 applicant teams at TEKNOFEST 2026

The SiliCore MCU is finished. It placed fourth out of 94 applicant teams in the Chip Design Competition — Microcontroller Design track.

Download the presentation PDF · 4 MB

32-bit CV32E40P RISC-V core

AXI4-Lite In-house interconnect

3 Implementation targets

3 Engineers

The architecture

A CV32E40P RISC-V core issuing memory-mapped reads and writes over an in-house AXI4-Lite fabric to a bank of custom peripherals.

Full breakdown

Block diagram of the SiliCore SoC: a CV32E40P core with a debug module and JTAG, an address decoder, boot ROM and debug ROM, instruction and data memory, an OBI-AXI bridge and AXI mux onto an AXI interconnect, an interrupt vector controller, and the QSPI, GPIO, timer, UART0, I2C and UART1 peripherals alongside the AI accelerator. — SiliCore SoC architecture.

Where we are

Two tracks running in parallel: our own hardware version history, and the competition stages. Both are finished — the hardware through its final ASIC run, the competition through the jury's decision.

MCU Versions

Team founded — 9 Aug 2025 — SiliCore established
demo_v01 — 15 Oct 2025 — First working bring-up
demo_v02 — 20 Dec 2025
demo_v04 — 21 Mar 2026 — Peripheral set working
SKY130 ASIC flow — 10 May 2026 — First hardened run, standalone MCU
demo_v06 — 28 Jul 2026 — IVC block and JTAG debugger
demo_v10 — 19 Aug 2026 — AI accelerator integrated into the MCU
SKY130 ASIC flow — final run — 11 Sep 2026 — Full top-level SoC hardened

TEKNOFEST 2026

OTR — Preliminary design report — 79.5 pts
DTR — Design technical report — 80.5 pts
Hardening — OpenLane RTL-to-GDS (done)
Final — Judged 4th of 94 teams

What we work on

Engineering write-ups on the parts of the chip we build ourselves.

All posts

MCU Design

RISC-V microcontroller subsystems end-to-end: AXI4-Lite fabric, clock/reset strategy, bring-up.

AI Accelerator

A custom neural-network inference engine with its own register interface and UART weight-loading path.

Debuggable MCU

JTAG, an interrupt vector controller and a pinmux — the hardware that makes bring-up something other than guesswork.

Verification

Two deliberately independent paths — SystemVerilog/UVM and a cocotb cross-check that caught a real bug.

Silicon: FPGA & ASIC

The same RTL built on Agilex 3 and Gowin FPGAs and carried through OpenLane to a hardened GDS.

High Performance, Cheap ASIC

Hardening the SoC on SKY130 with an entirely open flow — no tool licences, no PDK fees.

Implementations

One RTL description, built three ways — two FPGA families and an open-PDK ASIC flow.

FPGA

Altera Agilex 3

Built through Quartus Prime, from the same SystemVerilog that goes to OpenLane.

Gowin Tang Primer 20K

The low-cost target, with Gowin-specific HDMI and RAM IP wrappers.

ASIC

SkyWater SKY130A

The open 130nm PDK behind both hardened runs, through OpenLane.

The team

Three engineers at Hacettepe University, mostly self-taught in digital design.

Team page

Bekir Yufka

Bekir YUFKA

System Architect & Project Lead

Top-level synthesis of the MCU subsystem
System-wide UVM verification
AI accelerator designer

Eyüp Ertan Sağdış

Eyüp Ertan SAĞDIŞ

Core Design & Integration Engineer

AXI4 / AXI4-Lite interconnect architect
Most peripheral modules in SystemVerilog
ASIC flow — OpenLane on SKY130A

Arda Tecimen

Arda TECİMEN

Verification & Debug Infrastructure Engineer

Module-level SystemVerilog testbenches
UVM verification and top-level testbench
JTAG debug interface, IVC block, pinmux
Custom boot sequencing and init flows

Get in touch

For partnerships, collaboration, and media.

contact@silicore.com.tr